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Efficient bidirectional conversion between RM and DFRM expansions (2008)
Journal Article
Xu, H., Yang, M., & Almaini, A. E. A. (2008). Efficient bidirectional conversion between RM and DFRM expansions. The Mediterranean journal of electronics and communications, 4, 84-89

A number of different representations of the Boolean function are used in order to find a good circuit representation in terms of area, speed and power performance. In this paper, an effective decomposition method is proposed for the bidirectional tr... Read More about Efficient bidirectional conversion between RM and DFRM expansions.

Algorithms in computer-aided design of VLSI circuits. (2006)
Thesis
Yang, M. Algorithms in computer-aided design of VLSI circuits. (Thesis). Edinburgh Napier University. http://researchrepository.napier.ac.uk/id/eprint/6493

With the increased complexity of Very Large Scale Integrated (VLSI) circuits,
Computer Aided Design (CAD) plays an even more important role. Top-down
design methodology and layout of VLSI are reviewed. Moreover, previously
published algorithms in... Read More about Algorithms in computer-aided design of VLSI circuits..

A novel low power FSM partition approach and its implementation. (2005)
Journal Article
Xia, Y., Ye, X., Wang, L. Y., Tao, J., & Almaini, A. E. A. (2005). A novel low power FSM partition approach and its implementation. NORCHIP Conference, 102-105. https://doi.org/10.1109/NORCHP.2005.1596999

A new Finite State Machine (FSM) partioning approach is proposed in this paper. A genetic algorithm (GA) is employed to search the optimal or near optimal solution. A new cost function is used to guide the optimisation. The proposed algorithm is impl... Read More about A novel low power FSM partition approach and its implementation..

FPGA placement using genetic algorithm with simulated annealing. (2005)
Journal Article
Yang, M., Almaini, A. E. A., Wang, L. Y., & Wang, P. (2005). FPGA placement using genetic algorithm with simulated annealing. ASICON, 2, 808-811. https://doi.org/10.1109/ICASIC.2005.1611450

A mixed Genetic Algorithm and Simulated Annealing (GASA) algorithm is used for the placement of symmetrical FPGA. The prpoposed algortithm includes 2 stage processes. In the first stage process it optimizes placement solutions globally using GA. In t... Read More about FPGA placement using genetic algorithm with simulated annealing..

A novel multiple-valued CMOS flip-flop employing multiple-valued clock. (2005)
Journal Article
Xia, Y., Wang, L. Y., & Almaini, A. E. A. (2005). A novel multiple-valued CMOS flip-flop employing multiple-valued clock. Journal of Computer Science and Technology, 20, 237-242. https://doi.org/10.1007/s11390-005-0237-4

A new CMOS quaternary D flip-flop is implemented employing a multiple-valued clock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared with traditional multiple-valued flip-flops, the proposed multiple-valued CMOS fli... Read More about A novel multiple-valued CMOS flip-flop employing multiple-valued clock..

Evolutionary algorithms and their use in the design of sequential logic circuits. (2004)
Journal Article
Ali, B., Almaini, A. E. A., & Kalganova, T. (2004). Evolutionary algorithms and their use in the design of sequential logic circuits. Genetic Programming and Evolvable Machines, 5, 11-29. https://doi.org/10.1023/B%3AGENP.0000017009.11392.e2

In this paper an approach based on an evolutionary algorithm to design synchronous sequential logic circuits with minimum number of logic gates is suggested. The proposed method consists of four main stages. The first stage is concerned with the use... Read More about Evolutionary algorithms and their use in the design of sequential logic circuits..

Expansion of logical function in the OR-coincidence system and the transform between it and maxterm expansion. (2003)
Journal Article
Cheng, J., Chen, X., Faraj, K., & Almaini, A. E. A. (2003). Expansion of logical function in the OR-coincidence system and the transform between it and maxterm expansion. IEE proceedings. Computers and digital techniques, 150, 397-402. https://doi.org/10.1049/ip-cdt%3A20030969

Based on the features of coincidence operation, a canonical OR coincidence (COC) expansion of logical functions in the OR-coincidence algebraic system is proposed, and its mapping expression (dj-map) is given. Then two new operations are introduced a... Read More about Expansion of logical function in the OR-coincidence system and the transform between it and maxterm expansion..

Differential CMOS edge-triggered flip-flop with clock gating. (2002)
Journal Article
Xia, Y., & Almaini, A. E. A. (2002). Differential CMOS edge-triggered flip-flop with clock gating. Electronics Letters, 38, 9-11. https://doi.org/10.1049/el%3A20020038

A non-redundant transition clock chain is proposed and applied to differential edge-triggered flip-flops. PSPICE simulation shows that compared to a recently published design the proposed circuit can save power when switching activity of the input si... Read More about Differential CMOS edge-triggered flip-flop with clock gating..

Generalised Reed-Muller ASIC converter. (1996)
Presentation / Conference Contribution
Almaini, A. E. A., & Burnside, K. (1996, October). Generalised Reed-Muller ASIC converter

The paper outlines the design for a new IC for bidirectional conversion between the functional and operational domains of logic funcyions. The circuit can generate all fixed polarities of Generalised Reed-Muller expansions for a given Boolean express... Read More about Generalised Reed-Muller ASIC converter..

One-bit adder design based on Reed-Muller expansions (1995)
Journal Article
Guan, Z., & Almaini, A. E. A. (1995). One-bit adder design based on Reed-Muller expansions. International Journal of Electronics, 79(5), 519-529. https://doi.org/10.1080/00207219508926289

It has been claimed for some time that the Reed-Muller technique can yield a simpler arithmetic circuit if it is employed in the design procedure. In fact, no practical application in this field can be found in the open literature. This paper attempt... Read More about One-bit adder design based on Reed-Muller expansions.

Robot Calibration Using Artificial Neural Networks (1995)
Thesis
Zhong, X. Robot Calibration Using Artificial Neural Networks. (Thesis). Napier University. http://researchrepository.napier.ac.uk/Output/2254583

Robot calibration is an integrated procedure of measurement and data processing to improve and maintain robot positioning accuracy. Existing robot calibration techniques require extensive human intervention and off-line processing, which preclude the... Read More about Robot Calibration Using Artificial Neural Networks.

Using genetic algorithms for the variable ordering of Reed-Muller binary decision diagrams (1995)
Journal Article
Almaini, A. E. A., & Zhuang, N. (1995). Using genetic algorithms for the variable ordering of Reed-Muller binary decision diagrams. Microelectronics Journal, 26(5), 471-480. https://doi.org/10.1016/0026-2692%2895%2998949-R

Results are reported of the use of genetic algorithms for the variable ordering problem in Reed-Muller binary decision diagrams. Tests carried out on benchmark examples and randomly generated functions are very encouraging and compare favourably with... Read More about Using genetic algorithms for the variable ordering of Reed-Muller binary decision diagrams.

Logic synthesis and optimisation using Reed-Muller expansions (1995)
Thesis
McKenzie, L. M. Logic synthesis and optimisation using Reed-Muller expansions. (Thesis). Edinburgh Napier University. http://researchrepository.napier.ac.uk/id/eprint/4276

This thesis presents techniques and algorithms which may be employed to represent, generate and optimise particular categories of Exclusive-OR SumOf-Products (ESOP) forms. The work documented herein concentrates on two types of Reed-Muller (RM) expre... Read More about Logic synthesis and optimisation using Reed-Muller expansions.