Yinshui Xia
A novel multiple-valued CMOS flip-flop employing multiple-valued clock.
Xia, Yinshui; Wang, Lun Yao; Almaini, A E A
Authors
Lun Yao Wang
A E A Almaini
Abstract
A new CMOS quaternary D flip-flop is implemented employing a multiple-valued clock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared with traditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterised by improved storage capacity, flexible logic structure and reduced power dissipation.
Citation
Xia, Y., Wang, L. Y., & Almaini, A. E. A. (2005). A novel multiple-valued CMOS flip-flop employing multiple-valued clock. Journal of Computer Science and Technology, 20, 237-242. https://doi.org/10.1007/s11390-005-0237-4
| Journal Article Type | Article |
|---|---|
| Publication Date | 2005-03 |
| Deposit Date | May 7, 2009 |
| Print ISSN | 1000-9000 |
| Electronic ISSN | 1860-4749 |
| Publisher | BMC |
| Peer Reviewed | Peer Reviewed |
| Volume | 20 |
| Pages | 237-242 |
| DOI | https://doi.org/10.1007/s11390-005-0237-4 |
| Keywords | Integrated circuits; CMOS; Flip-flop circuits; Multiple-valued clock; Computer systems; Computer logic; Performance evaluation; |
| Public URL | http://researchrepository.napier.ac.uk/id/eprint/2567 |
| Publisher URL | http://dx.doi.org/10.1007/s11390-005-0237-4 |