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Differential CMOS edge-triggered flip-flop with clock gating.

Xia, Yinshui; Almaini, A E A

Authors

Yinshui Xia

A E A Almaini



Abstract

A non-redundant transition clock chain is proposed and applied to differential edge-triggered flip-flops. PSPICE simulation shows that compared to a recently published design the proposed circuit can save power when switching activity of the input signal

Citation

Xia, Y., & Almaini, A. E. A. (2002). Differential CMOS edge-triggered flip-flop with clock gating. Electronics Letters, 38, 9-11. https://doi.org/10.1049/el%3A20020038

Journal Article Type Article
Publication Date Jan 3, 2002
Deposit Date May 14, 2009
Print ISSN 0013-5194
Electronic ISSN 1350-911X
Publisher Institution of Engineering and Technology (IET)
Peer Reviewed Peer Reviewed
Volume 38
Pages 9-11
DOI https://doi.org/10.1049/el%3A20020038
Keywords CMOS integrated circuits; Flip-flops; Edge-trigger; PSPICE simulation; Power saving;
Public URL http://researchrepository.napier.ac.uk/id/eprint/2594
Publisher URL http://dx.doi.org/10.1049/el:20020038



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