Differential CMOS edge-triggered flip-flop with clock gating. (2002)
Journal Article
Xia, Y., & Almaini, A. E. A. (2002). Differential CMOS edge-triggered flip-flop with clock gating. Electronics Letters, 38, 9-11. https://doi.org/10.1049/el%3A20020038

A non-redundant transition clock chain is proposed and applied to differential edge-triggered flip-flops. PSPICE simulation shows that compared to a recently published design the proposed circuit can save power when switching activity of the input si... Read More about Differential CMOS edge-triggered flip-flop with clock gating..