Outputs (36)

Reversed ROBDD circuits. (1998)
Journal Article
Bystrov, A., & Almaini, A. E. A. (1998). Reversed ROBDD circuits. Electronics Letters, 34, 1447-1449. https://doi.org/10.1049/el%3A19981070

A new class of logic circuits is proposed. Being derived from reduced ordered binary decision diagrams, these circuits inherit compactness and the ability to represent very large switching functions. The reveresed signal propagation results in low d... Read More about Reversed ROBDD circuits..

A semicustom IC for generating optimum generalized Reed-Muller expansions (1997)
Journal Article
Almaini, A. E. A. (1997). A semicustom IC for generating optimum generalized Reed-Muller expansions. Microelectronics Journal, 28(2), 129-142. https://doi.org/10.1016/s0026-2692%2896%2900087-0

The paper explains the theory and design of a semi-custom integrated circuit (IC) for the generation of optimum polarity of a given Boolean function. Given the minterm coefficients of all the fixed polarities of the generalized Reed-Muller expansions... Read More about A semicustom IC for generating optimum generalized Reed-Muller expansions.

Generalised Reed-Muller ASIC converter. (1996)
Presentation / Conference Contribution
Almaini, A. E. A., & Burnside, K. (1996). Generalised Reed-Muller ASIC converter. In 2nd International Conference on ASIC (73-76). https://doi.org/10.1109/ICASIC.1996.562754

The paper outlines the design for a new IC for bidirectional conversion between the functional and operational domains of logic funcyions. The circuit can generate all fixed polarities of Generalised Reed-Muller expansions for a given Boolean express... Read More about Generalised Reed-Muller ASIC converter..

One-bit adder design based on Reed-Muller expansions (1995)
Journal Article
Guan, Z., & Almaini, A. E. A. (1995). One-bit adder design based on Reed-Muller expansions. International Journal of Electronics, 79(5), 519-529. https://doi.org/10.1080/00207219508926289

It has been claimed for some time that the Reed-Muller technique can yield a simpler arithmetic circuit if it is employed in the design procedure. In fact, no practical application in this field can be found in the open literature. This paper attempt... Read More about One-bit adder design based on Reed-Muller expansions.

Using genetic algorithms for the variable ordering of Reed-Muller binary decision diagrams (1995)
Journal Article
Almaini, A. E. A., & Zhuang, N. (1995). Using genetic algorithms for the variable ordering of Reed-Muller binary decision diagrams. Microelectronics Journal, 26(5), 471-480. https://doi.org/10.1016/0026-2692%2895%2998949-R

Results are reported of the use of genetic algorithms for the variable ordering problem in Reed-Muller binary decision diagrams. Tests carried out on benchmark examples and randomly generated functions are very encouraging and compare favourably with... Read More about Using genetic algorithms for the variable ordering of Reed-Muller binary decision diagrams.

Parallel CMOS 2's complement multiplier based on 5:3 counter. (1994)
Presentation / Conference Contribution
Guan, Z., Thomson, P., & Almaini, A. E. A. (1994). Parallel CMOS 2's complement multiplier based on 5:3 counter. In IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings. (298-301). https://doi.or

A parallel 8x8 2's complement multiplier based on a novel 5:3 counter is presented. The structure of the multiplier is simple, regular and very suitable for VLSI implementation. Compared with Wallace tree and Redundant Bimary Addition Tree, the propo... Read More about Parallel CMOS 2's complement multiplier based on 5:3 counter..