Parallel CMOS 2's complement multiplier based on 5:3 counter.

Guan, Zhicheng; Thomson, P; Almaini, A E A

Abstract

A parallel 8x8 2's complement multiplier based on a novel 5:3 counter is presented. The structure of the multiplier is simple, regular and very suitable for VLSI implementation. Compared with Wallace tree and Redundant Bimary Addition Tree, the proposed scheme requires less levels for the same number of partial products, resulting in a simpler and faster circuit.

Citation

Guan, Z., Thomson, P., & Almaini, A. E. A. (1994, October). Parallel CMOS 2's complement multiplier based on 5:3 counter

• Start Date: Oct 10, 1994
• End Date: Oct 12, 1994
• Publication Date: 1994-10
• Deposit Date: Jun 1, 2009
• Peer Reviewed: Peer Reviewed
• Pages: 298-301
• Book Title: IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings..
• ISBN: 0-8186-6565-3
• DOI: https://doi.org/10.1109/ICCD.1994.331910
• Keywords: Integrated circuits; CMOS; Computing; Parallel processing; Tree structures; VLSI circuits
• Public URL: http://researchrepository.napier.ac.uk/id/eprint/2624
• Publisher URL: http://dx.doi.org/10.1109/ICCD.1994.331910