Outputs (7)

An evolutionary approach for symmetrical field programmable gate array placement. (2005)
Presentation / Conference Contribution
Yang, M., Almaini, A. E. A., Wang, L. Y., & Wang, P. (2005). An evolutionary approach for symmetrical field programmable gate array placement. In Research in Microelectronics and Electronics, 2005 PhD (169-172). https://doi.org/10.1109/RME.2005.1543030

An evolutionary computation method is used to place a set of different Microelectronics Center of North Carolina (MCNC) benchmark circuits on traditional symmetrical Field Programmable Gate Array (FPGA). The experimental results are compared to the s... Read More about An evolutionary approach for symmetrical field programmable gate array placement..

A novel low power FSM partition approach and its implementation. (2005)
Journal Article
Xia, Y., Ye, X., Wang, L. Y., Tao, J., & Almaini, A. E. A. (2005). A novel low power FSM partition approach and its implementation. NORCHIP Conference, 102-105. https://doi.org/10.1109/NORCHP.2005.1596999

A new Finite State Machine (FSM) partioning approach is proposed in this paper. A genetic algorithm (GA) is employed to search the optimal or near optimal solution. A new cost function is used to guide the optimisation. The proposed algorithm is impl... Read More about A novel low power FSM partition approach and its implementation..

Fast tabular based conversion methods for Canonical OR-Coincidence. (2005)
Presentation / Conference Contribution
Yang, M., Wang, P., Chen, X., & Almaini, A. E. A. (2005). Fast tabular based conversion methods for Canonical OR-Coincidence. In EUROCON 2005 - The International Conference on Computer as a Tool (507-510). https://doi.org/10.1109/EURCON.2005.1629976

Two fast conversion alogorithms based on tabular technique for Canonical OR-Coincidence (COC) expansions are introduced. By using bitwise operations, the Serial Tabular Technique (STT) can achieve speed of less than 2 seconds for 21 variables for ran... Read More about Fast tabular based conversion methods for Canonical OR-Coincidence..

Five-valued circuit quantitative theory and design of five-valued twisted-ring. (2005)
Presentation / Conference Contribution
Wang, P., Liu, Y., Yang, M., & Almaini, A. E. A. (2005). Five-valued circuit quantitative theory and design of five-valued twisted-ring. In T. Tang, & Y. Huang (Eds.), ASICON 2005: Proceedings of the 6th International Conference on ASIC, 2005 (354-357). h

This paper presents a six-valued algebra in order to form the theory of three essential elements for five-valued circuits, which is a mathematical tool for quantitative investigation on five-valued circuits. Based on the theory, the component level c... Read More about Five-valued circuit quantitative theory and design of five-valued twisted-ring..

Novel synthesis method of mixed polarity reed-muller functions. (2005)
Presentation / Conference Contribution
Xia, Y., Ye, X., Wang, L. Y., Zou, Z., & Almaini, A. E. A. (2005). Novel synthesis method of mixed polarity reed-muller functions.

In this paper a new approach is proposed to obtain a compact mixed polarity Reed-Muller form, starting from a fixed polarity Reed-Muller expression; a fixed polarity Reed-Muller function is expressed into a truth vector, the truth vector is shrunk an... Read More about Novel synthesis method of mixed polarity reed-muller functions..

FPGA placement using genetic algorithm with simulated annealing. (2005)
Journal Article
Yang, M., Almaini, A. E. A., Wang, L. Y., & Wang, P. (2005). FPGA placement using genetic algorithm with simulated annealing. ASICON, 2, 808-811. https://doi.org/10.1109/ICASIC.2005.1611450

A mixed Genetic Algorithm and Simulated Annealing (GASA) algorithm is used for the placement of symmetrical FPGA. The prpoposed algortithm includes 2 stage processes. In the first stage process it optimizes placement solutions globally using GA. In t... Read More about FPGA placement using genetic algorithm with simulated annealing..

A novel multiple-valued CMOS flip-flop employing multiple-valued clock. (2005)
Journal Article
Xia, Y., Wang, L. Y., & Almaini, A. E. A. (2005). A novel multiple-valued CMOS flip-flop employing multiple-valued clock. Journal of Computer Science and Technology, 20, 237-242. https://doi.org/10.1007/s11390-005-0237-4

A new CMOS quaternary D flip-flop is implemented employing a multiple-valued clock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared with traditional multiple-valued flip-flops, the proposed multiple-valued CMOS fli... Read More about A novel multiple-valued CMOS flip-flop employing multiple-valued clock..