Parallel CMOS 2's complement multiplier based on 5:3 counter.
(1994)
Presentation / Conference Contribution
Guan, Z., Thomson, P., & Almaini, A. E. A. (1994). Parallel CMOS 2's complement multiplier based on 5:3 counter. In IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings. (298-301). https://doi.or
A parallel 8x8 2's complement multiplier based on a novel 5:3 counter is presented. The structure of the multiplier is simple, regular and very suitable for VLSI implementation. Compared with Wallace tree and Redundant Bimary Addition Tree, the propo... Read More about Parallel CMOS 2's complement multiplier based on 5:3 counter..