All Outputs (3)

A novel low power FSM partition approach and its implementation. (2005)
Journal Article
Xia, Y., Ye, X., Wang, L. Y., Tao, J., & Almaini, A. E. A. (2005). A novel low power FSM partition approach and its implementation. NORCHIP Conference, 102-105. https://doi.org/10.1109/NORCHP.2005.1596999

A new Finite State Machine (FSM) partioning approach is proposed in this paper. A genetic algorithm (GA) is employed to search the optimal or near optimal solution. A new cost function is used to guide the optimisation. The proposed algorithm is impl... Read More about A novel low power FSM partition approach and its implementation..

FPGA placement using genetic algorithm with simulated annealing. (2005)
Journal Article
Yang, M., Almaini, A. E. A., Wang, L. Y., & Wang, P. (2005). FPGA placement using genetic algorithm with simulated annealing. ASICON, 2, 808-811. https://doi.org/10.1109/ICASIC.2005.1611450

A mixed Genetic Algorithm and Simulated Annealing (GASA) algorithm is used for the placement of symmetrical FPGA. The prpoposed algortithm includes 2 stage processes. In the first stage process it optimizes placement solutions globally using GA. In t... Read More about FPGA placement using genetic algorithm with simulated annealing..

A novel multiple-valued CMOS flip-flop employing multiple-valued clock. (2005)
Journal Article
Xia, Y., Wang, L. Y., & Almaini, A. E. A. (2005). A novel multiple-valued CMOS flip-flop employing multiple-valued clock. Journal of Computer Science and Technology, 20, 237-242. https://doi.org/10.1007/s11390-005-0237-4

A new CMOS quaternary D flip-flop is implemented employing a multiple-valued clock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared with traditional multiple-valued flip-flops, the proposed multiple-valued CMOS fli... Read More about A novel multiple-valued CMOS flip-flop employing multiple-valued clock..