Outputs (4)

Exact minimisation of large multiple output FPRM functions. (2002)
Journal Article
Almaini, A. E. A., & Wang, L. Y. (2002). Exact minimisation of large multiple output FPRM functions. IEE proceedings. Computers and digital techniques, 149, 203-212. https://doi.org/10.1049/ip-cdt%3A20020674

The properties of the polarity for sum-of-products (SOP) expressions of Boolean functions are formally investigated. A transform matrix S is developed to convert SOP expressions from one polarity to another polarity. It is shown that the effect of SO... Read More about Exact minimisation of large multiple output FPRM functions..

Genetic algorithm based state assignment for power and area optimisation. (2002)
Journal Article
Xia, Y., & Almaini, A. E. A. (2002). Genetic algorithm based state assignment for power and area optimisation. IEE proceedings. Computers and digital techniques, 149, 128-133. https://doi.org/10.1049/ip-cdt%3A20020431

The use of assignment to minimise power dissipation and area for finite-state machines is computationally difficult. Most published results show that the reduction of switching activity often trades with area penalty. Two cost functions are introduce... Read More about Genetic algorithm based state assignment for power and area optimisation..

Optimisation of Reed-Muller PLA implementations. (2002)
Journal Article
Wang, L. Y., & Almaini, A. E. A. (2002). Optimisation of Reed-Muller PLA implementations. IEE proceedings. Circuits, devices, and systems, 149, 119-128. https://doi.org/10.1049/ip-cds%3A20020354

Decomposition techniques are utilised for mixed polarity Reed-Muller minimisation, which lead to Reed-Muller programmable logic array implementations for Boolean functions. The proposed algorithm produces a simplified mixed polarity Reed-Muller forma... Read More about Optimisation of Reed-Muller PLA implementations..

Differential CMOS edge-triggered flip-flop with clock gating. (2002)
Journal Article
Xia, Y., & Almaini, A. E. A. (2002). Differential CMOS edge-triggered flip-flop with clock gating. Electronics Letters, 38, 9-11. https://doi.org/10.1049/el%3A20020038

A non-redundant transition clock chain is proposed and applied to differential edge-triggered flip-flops. PSPICE simulation shows that compared to a recently published design the proposed circuit can save power when switching activity of the input si... Read More about Differential CMOS edge-triggered flip-flop with clock gating..