Outputs (40)

Five-valued circuit quantitative theory and design of five-valued twisted-ring. (2005)
Presentation / Conference Contribution
Wang, P., Liu, Y., Yang, M., & Almaini, A. E. A. (2005). Five-valued circuit quantitative theory and design of five-valued twisted-ring. In T. Tang, & Y. Huang (Eds.), ASICON 2005: Proceedings of the 6th International Conference on ASIC, 2005 (354-357). h

This paper presents a six-valued algebra in order to form the theory of three essential elements for five-valued circuits, which is a mathematical tool for quantitative investigation on five-valued circuits. Based on the theory, the component level c... Read More about Five-valued circuit quantitative theory and design of five-valued twisted-ring..

FPGA placement using genetic algorithm with simulated annealing. (2005)
Journal Article
Yang, M., Almaini, A. E. A., Wang, L. Y., & Wang, P. (2005). FPGA placement using genetic algorithm with simulated annealing. ASICON, 2, 808-811. https://doi.org/10.1109/ICASIC.2005.1611450

A mixed Genetic Algorithm and Simulated Annealing (GASA) algorithm is used for the placement of symmetrical FPGA. The prpoposed algortithm includes 2 stage processes. In the first stage process it optimizes placement solutions globally using GA. In t... Read More about FPGA placement using genetic algorithm with simulated annealing..

A novel multiple-valued CMOS flip-flop employing multiple-valued clock. (2005)
Journal Article
Xia, Y., Wang, L. Y., & Almaini, A. E. A. (2005). A novel multiple-valued CMOS flip-flop employing multiple-valued clock. Journal of Computer Science and Technology, 20, 237-242. https://doi.org/10.1007/s11390-005-0237-4

A new CMOS quaternary D flip-flop is implemented employing a multiple-valued clock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared with traditional multiple-valued flip-flops, the proposed multiple-valued CMOS fli... Read More about A novel multiple-valued CMOS flip-flop employing multiple-valued clock..

Evolutionary algorithms and their use in the design of sequential logic circuits. (2004)
Journal Article
Ali, B., Almaini, A. E. A., & Kalganova, T. (2004). Evolutionary algorithms and their use in the design of sequential logic circuits. Genetic Programming and Evolvable Machines, 5, 11-29. https://doi.org/10.1023/B%3AGENP.0000017009.11392.e2

In this paper an approach based on an evolutionary algorithm to design synchronous sequential logic circuits with minimum number of logic gates is suggested. The proposed method consists of four main stages. The first stage is concerned with the use... Read More about Evolutionary algorithms and their use in the design of sequential logic circuits..

Expansion of logical function in the OR-coincidence system and the transform between it and maxterm expansion. (2003)
Journal Article
Cheng, J., Chen, X., Faraj, K., & Almaini, A. E. A. (2003). Expansion of logical function in the OR-coincidence system and the transform between it and maxterm expansion. IEE proceedings. Computers and digital techniques, 150, 397-402. https://doi.org/10.1049/ip-cdt%3A20030969

Based on the features of coincidence operation, a canonical OR coincidence (COC) expansion of logical functions in the OR-coincidence algebraic system is proposed, and its mapping expression (dj-map) is given. Then two new operations are introduced a... Read More about Expansion of logical function in the OR-coincidence system and the transform between it and maxterm expansion..

Multilevel logic simplification based on containment recursive paradigm. (2003)
Journal Article
Wang, L. Y., & Almaini, A. E. A. (2003). Multilevel logic simplification based on containment recursive paradigm. IEE proceedings. Computers and digital techniques, 150, 218-226. https://doi.org/10.1049/ip-cdt%3A20030575

This paper addresses a number of fundamental concepts and a novel technique for optimising practical multi-level designs for completely and incompletely specified multi-output functions. Multi-level design is the preferred approach in complex VSLI ci... Read More about Multilevel logic simplification based on containment recursive paradigm..

Power minimization of FPRM functions based on polarity conversion (2003)
Journal Article
Xia, Y., Wu, X., & Almaini, A. E. A. (2003). Power minimization of FPRM functions based on polarity conversion. Journal of Computer Science and Technology, 18(3), 325-331. https://doi.org/10.1007/BF02948902

For an n-variable Boolean function, there are 2[to the nth power] fixed polarity Reed-Muller (FPRM) forms. In this paper, a frame of power dissipation estimation for FPRM functions is presented and the polarity conversion is introduced to minimize th... Read More about Power minimization of FPRM functions based on polarity conversion.

Area and power optimization of FPRM function based circuits. (2003)
Presentation / Conference Contribution
Xia, Y., Ali, B., & Almaini, A. E. A. (2003). Area and power optimization of FPRM function based circuits. In Proceedings of the 2003 IEEE INternational Symposium on Circuits and Systems (V329-V332). https://doi.org/10.1109/ISCAS.2003.1206270

In this paper a frame of power dissipation estimation for FPRM function based circuits is presented and polarity conversion is proposed to optimize power and area for FPRM functions. Based on searching optimized polarity, an optimized algotithm is pr... Read More about Area and power optimization of FPRM function based circuits..

Exact minimisation of large multiple output FPRM functions. (2002)
Journal Article
Almaini, A. E. A., & Wang, L. Y. (2002). Exact minimisation of large multiple output FPRM functions. IEE proceedings. Computers and digital techniques, 149, 203-212. https://doi.org/10.1049/ip-cdt%3A20020674

The properties of the polarity for sum-of-products (SOP) expressions of Boolean functions are formally investigated. A transform matrix S is developed to convert SOP expressions from one polarity to another polarity. It is shown that the effect of SO... Read More about Exact minimisation of large multiple output FPRM functions..

Genetic algorithm based state assignment for power and area optimisation. (2002)
Journal Article
Xia, Y., & Almaini, A. E. A. (2002). Genetic algorithm based state assignment for power and area optimisation. IEE proceedings. Computers and digital techniques, 149, 128-133. https://doi.org/10.1049/ip-cdt%3A20020431

The use of assignment to minimise power dissipation and area for finite-state machines is computationally difficult. Most published results show that the reduction of switching activity often trades with area penalty. Two cost functions are introduce... Read More about Genetic algorithm based state assignment for power and area optimisation..