Reconfigurable neurons - making the most of configurable logic blocks (CLBs)

Ghani, Arfan; See, Chan H.; Migdadi, Hassan; Asif, Rameez; Abd-Alhameed, Raed A.A.; Noras, James M.

Abstract

An area-efficient hardware architecture is used to map fully parallel cortical columns on Field Programmable Gate Arrays (FPGA) is presented in this paper. To demonstrate the concept of this work, the proposed architecture is shown at the system level and benchmarked with image and speech recognition applications. Due to the spatio-temporal nature of spiking neurons, this has allowed such architectures to map on FPGAs in which communication can be performed through the use of spikes and signal can be represented in binary form. The process and viability of designing and implementing the multiple recurrent neural reservoirs with a novel multiplier-less reconfigurable architectures is described.

Citation

Ghani, A., See, C. H., Migdadi, H., Asif, R., Abd-Alhameed, R. A., & Noras, J. M. (2015, September). Reconfigurable neurons - making the most of configurable logic blocks (CLBs). Presented at 2015 Internet Technologies and Applications (ITA), Wrexham, United Kingdom

• Presentation Conference Type: Conference Paper (published)
• Conference Name: 2015 Internet Technologies and Applications (ITA)
• Start Date: Sep 8, 2015
• End Date: Sep 11, 2015
• Acceptance Date: Jun 15, 2015
• Online Publication Date: Nov 5, 2015
• Publication Date: 2015-09
• Deposit Date: May 29, 2019
• Publisher: Institute of Electrical and Electronics Engineers
• ISBN: 9781479980369
• DOI: https://doi.org/10.1109/itecha.2015.7317451
• Keywords: recurrent neural networks, reservior computing, reconfigurable computing, FPGAs, neural signal processing
• Public URL: http://researchrepository.napier.ac.uk/Output/1836856