A GALS Infrastructure for a Massively Parallel Multiprocessor

Plana, Luis A.; Furber, Steve B.; Temple, Steve; Khan, Mukaram; Shi, Yebin; Wu, Jian; Yang, Shufan

Abstract

This case study focuses on a massively parallel multiprocessor for real-time simulation of billions of neurons. Every node of the design comprises 20 ARM9 cores, a memory interface, a multicast router, and two NoC structures for communicating between internal cores and the environment. The NoCs are asynchronous; the cores and RAM interfaces are synchronous. This GALS approach decouples clocking concerns for different parts of the die, leading to greater power efficiency.

Citation

Plana, L. A., Furber, S. B., Temple, S., Khan, M., Shi, Y., Wu, J., & Yang, S. (2007). A GALS Infrastructure for a Massively Parallel Multiprocessor. IEEE Design and Test of Computers, 24(5), 454-463. https://doi.org/10.1109/mdt.2007.149

• Journal Article Type: Article
• Online Publication Date: Oct 8, 2007
• Publication Date: 2007-10
• Deposit Date: Mar 11, 2021
• Journal: IEEE Design & Test of Computers
• Print ISSN: 0740-7475
• Publisher: Institute of Electrical and Electronics Engineers
• Peer Reviewed: Peer Reviewed
• Volume: 24
• Issue: 5
• Pages: 454-463
• DOI: https://doi.org/10.1109/mdt.2007.149
• Public URL: http://researchrepository.napier.ac.uk/Output/2752415