All Outputs (11)

Minimization of incompletely specified mixed polarity Reed Muller functions using genetic algorithm. (2009)
Conference Proceeding
Al-Jassani, B. A., Urquhart, N. B., & Almaini, A. E. A. (2009). Minimization of incompletely specified mixed polarity Reed Muller functions using genetic algorithm. . https://doi.org/10.1109/12.67320

A New and efficient Genetic Algorithm (GA) based approach is presented to minimise the number of terms of Mixed Polarity Reed Muller (MPRM) single and multi output incompletely specified Boolean functions. The algorithm determines the allocation of d... Read More about Minimization of incompletely specified mixed polarity Reed Muller functions using genetic algorithm..

An efficient transformation method for DFRM expansions. (2007)
Conference Proceeding
Xu, H., Yang, M., Wang, L. Y., Tong, J. R., & Almaini, A. E. A. (2007). An efficient transformation method for DFRM expansions. In 7th International Conference on ASIC, 2007. ASICON '07 (1158-1161). https://doi.org/10.1109/ICASIC.2007.4415839

Dual Form of Reed-Muller (DFRM) expansions with fixed poarity are derived from Reed-Muller (RM) expansions by using the operation of Kronecker matrix products. An efficient decomposition method is proposed based on the formulation. The method can be... Read More about An efficient transformation method for DFRM expansions..

Adaptive PN code acquisition in multi-path spread spectrum communications using FPGA. (2007)
Conference Proceeding
Wei, B., Sharif, M., Binnie, D., & Almaini, A. E. A. (2007). Adaptive PN code acquisition in multi-path spread spectrum communications using FPGA. In Proceedings of the 13th International Symposium on Signals, Circuits and Systems (573-576)

Performance of two pseudonoise (PN) code detectors was tested. Cell averaging (CA) and order Statistics (OS) constant false alarm rates (CFAR) were analysed against mean acquisition time (MAT) and against the probability of detection (Pd). Both detec... Read More about Adaptive PN code acquisition in multi-path spread spectrum communications using FPGA..

PN code acquisition with a CA-CFAR adaptive digital matched filter and its realisation using FPGA. (2006)
Conference Proceeding
Wie, B., Sharif, M., Almaini, A. E. A., & Binnie, D. (2006). PN code acquisition with a CA-CFAR adaptive digital matched filter and its realisation using FPGA. In Proceedings of IEEE 13th International Conference on Systems, Signals & Image Processing, IWSSIP’06

In this paper the performance of a Cell Averaging Constant False Alarm Rate (CA-CFAR) Pseudo-Noise (PN) code adaptive detector is analysed for a single path communication channel. The detection process uses a digital Matched Filter (MF) and is implem... Read More about PN code acquisition with a CA-CFAR adaptive digital matched filter and its realisation using FPGA..

An evolutionary approach for symmetrical field programmable gate array placement. (2005)
Conference Proceeding
Yang, M., Almaini, A. E. A., Wang, L. Y., & Wang, P. (2005). An evolutionary approach for symmetrical field programmable gate array placement. In Research in Microelectronics and Electronics, 2005 PhD (169-172). https://doi.org/10.1109/RME.2005.1543030

An evolutionary computation method is used to place a set of different Microelectronics Center of North Carolina (MCNC) benchmark circuits on traditional symmetrical Field Programmable Gate Array (FPGA). The experimental results are compared to the s... Read More about An evolutionary approach for symmetrical field programmable gate array placement..

Fast tabular based conversion methods for Canonical OR-Coincidence. (2005)
Conference Proceeding
Yang, M., Wang, P., Chen, X., & Almaini, A. E. A. (2005). Fast tabular based conversion methods for Canonical OR-Coincidence. In EUROCON 2005 - The International Conference on Computer as a Tool (507-510). https://doi.org/10.1109/EURCON.2005.1629976

Two fast conversion alogorithms based on tabular technique for Canonical OR-Coincidence (COC) expansions are introduced. By using bitwise operations, the Serial Tabular Technique (STT) can achieve speed of less than 2 seconds for 21 variables for ran... Read More about Fast tabular based conversion methods for Canonical OR-Coincidence..

Five-valued circuit quantitative theory and design of five-valued twisted-ring. (2005)
Conference Proceeding
Wang, P., Liu, Y., Yang, M., & Almaini, A. E. A. (2005). Five-valued circuit quantitative theory and design of five-valued twisted-ring. In T. Tang, & Y. Huang (Eds.), ASICON 2005: Proceedings of the 6th International Conference on ASIC, 2005 (354-357). https://doi.org/10.1109/ICASIC.2005.1611323

This paper presents a six-valued algebra in order to form the theory of three essential elements for five-valued circuits, which is a mathematical tool for quantitative investigation on five-valued circuits. Based on the theory, the component level c... Read More about Five-valued circuit quantitative theory and design of five-valued twisted-ring..

Novel synthesis method of mixed polarity reed-muller functions. (2005)
Conference Proceeding
Xia, Y., Ye, X., Wang, L. Y., Zou, Z., & Almaini, A. E. A. (2005). Novel synthesis method of mixed polarity reed-muller functions.

In this paper a new approach is proposed to obtain a compact mixed polarity Reed-Muller form, starting from a fixed polarity Reed-Muller expression; a fixed polarity Reed-Muller function is expressed into a truth vector, the truth vector is shrunk an... Read More about Novel synthesis method of mixed polarity reed-muller functions..

Area and power optimization of FPRM function based circuits. (2003)
Conference Proceeding
Xia, Y., Ali, B., & Almaini, A. E. A. (2003). Area and power optimization of FPRM function based circuits. In Proceedings of the 2003 IEEE INternational Symposium on Circuits and Systems (V329-V332). https://doi.org/10.1109/ISCAS.2003.1206270

In this paper a frame of power dissipation estimation for FPRM function based circuits is presented and polarity conversion is proposed to optimize power and area for FPRM functions. Based on searching optimized polarity, an optimized algotithm is pr... Read More about Area and power optimization of FPRM function based circuits..

Generalised Reed-Muller ASIC converter. (1996)
Conference Proceeding
Almaini, A. E. A., & Burnside, K. (1996). Generalised Reed-Muller ASIC converter. In 2nd International Conference on ASIC (73-76). https://doi.org/10.1109/ICASIC.1996.562754

The paper outlines the design for a new IC for bidirectional conversion between the functional and operational domains of logic funcyions. The circuit can generate all fixed polarities of Generalised Reed-Muller expansions for a given Boolean express... Read More about Generalised Reed-Muller ASIC converter..

Parallel CMOS 2's complement multiplier based on 5:3 counter. (1994)
Conference Proceeding
Guan, Z., Thomson, P., & Almaini, A. E. A. (1994). Parallel CMOS 2's complement multiplier based on 5:3 counter. In IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings. (298-301). https://doi.org/10.1109/ICCD.1994.331910

A parallel 8x8 2's complement multiplier based on a novel 5:3 counter is presented. The structure of the multiplier is simple, regular and very suitable for VLSI implementation. Compared with Wallace tree and Redundant Bimary Addition Tree, the propo... Read More about Parallel CMOS 2's complement multiplier based on 5:3 counter..