Computer aided synthesis and optimisation of electronic logic circuits
(2011)
Thesis
Al-Jassani, B. A. Computer aided synthesis and optimisation of electronic logic circuits. (Thesis). Edinburgh Napier University. Retrieved from http://researchrepository.napier.ac.uk/id/eprint/6658
In this thesis, a variety of algorithms for synthesis and optimisation of combinational and sequential logic circuits are developed. These algorithms could be part of new commercial EGAD package for future VLSI digital designs. The results show that... Read More about Computer aided synthesis and optimisation of electronic logic circuits.