Comparative study on connected component labeling algorithms for embedded video processing systems.

Walczyk, Robert; Armitage, Alistair; Binnie, David

Abstract

The objective of this paper is to carry out a detailed analysis of the most popular connected components labeling (CCL) algorithms for binary images. This study investigates their usability for processing streaming data and suitability for implementation using Field-Programmable Gate Array (FPGA) devices. The first part of this paper presents the state of the art on CCL algorithms. Both capability for real-time video processing as well as memory requirements are taken into consideration. The second part of the paper describes an efficient implementation of the single pass labeling algorithm using a Virtex-II Pro FPGA. It is verified on the development board with an infrared camera module as a real-time video source. The system is capable of processing video stream with 640 x 480 pixels per frame at a speed of 30 fps limited by the bandwidth of the video source.

Citation

Walczyk, R., Armitage, A., & Binnie, D. (2010). Comparative study on connected component labeling algorithms for embedded video processing systems. In H. Deligiannidis (Ed.), Proceedings of the IPCV'10

• Conference Name: The 2010 International Conference on Image Processing, Computer Vision, and Pattern Recognition
• Start Date: Jul 12, 2010
• End Date: Jul 15, 2010
• Publication Date: Jul 12, 2010
• Deposit Date: Jan 31, 2011
• Publicly Available Date: Jan 31, 2011
• Peer Reviewed: Peer Reviewed
• Volume: 2
• Book Title: Proceedings of the IPCV'10
• ISBN: 1-60132-153-8
• Keywords: Connected component labelling; FPGA; embedded systems
• Public URL: http://researchrepository.napier.ac.uk/id/eprint/3901