Comparative study on connected component labeling algorithms for embedded video processing systems.
Walczyk, Robert; Armitage, Alistair; Binnie, David
Dr David Binnie D.Binnie@napier.ac.uk
The objective of this paper is to carry out a detailed analysis of the most popular connected components labeling (CCL) algorithms for binary images. This study investigates their usability for processing streaming data and suitability for implementation using Field-Programmable Gate Array (FPGA) devices. The first part of this paper presents the state of the art on CCL algorithms. Both capability for real-time video processing as well as memory requirements are taken into consideration. The second part of the paper describes an efficient implementation of the single pass labeling algorithm using a Virtex-II Pro FPGA. It is verified on the development board with an infrared camera module as a real-time video source. The system is capable of processing video stream with 640 x 480 pixels per frame at a speed of 30 fps limited by the bandwidth of the video source.
Walczyk, R., Armitage, A., & Binnie, D. (2010). Comparative study on connected component labeling algorithms for embedded video processing systems. In H. Deligiannidis (Ed.), Proceedings of the IPCV'10
|Conference Name||The 2010 International Conference on Image Processing, Computer Vision, and Pattern Recognition|
|Start Date||Jul 12, 2010|
|End Date||Jul 15, 2010|
|Publication Date||Jul 12, 2010|
|Deposit Date||Jan 31, 2011|
|Publicly Available Date||Jan 31, 2011|
|Peer Reviewed||Peer Reviewed|
|Book Title||Proceedings of the IPCV'10|
|Keywords||Connected component labelling; FPGA; embedded systems;|
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